1. Field of the Invention
This invention generally relates to a method and an apparatus for processing digital signals. More particularly, the present invention relates to a digital signal processing apparatus and a digital signal processing method for conducting a signal switching process on ΔΣ-modulated digital audio signals.
This application claims priority of Japanese Patent Application No. 2004-087721, filed on Mar. 24, 2004, the entirety of which is incorporated herein by reference.
2. Description of Related Art
Delta-sigma (ΔΣ)-modulated high speed 1-bit signals are characterized by a very high sampling frequency and a short data word length if compared with conventional so-called multi-bit digital signals that have been and are being used for digital audio applications. More specifically, such a 1-bit signal has a sampling frequency sixty four (64) times higher than that of a multi-bit digital signal whose sampling frequency and data word length are respectively 44.1 kHz and 16 bits. Additionally, such a signal can ensure a high dynamic range in the conventional audio band (20 kHz) that is a low band relative to the excessively high sampling frequency of sixty four times of the conventional sampling frequency due to ΣΔ modulation if it is a 1-bit signal. Thus, such 1-bit signals can find applications in the field of high sound quality recorders and that of data transmission by effectively exploiting the characteristic properties.
FIG. 1 of the accompanying drawings schematically illustrates the configuration of a 1-bit ΔΣ modulator 60 for generating a 1-bit audio data. The ΔΣ modulator 60 comprises an adder 62, an integrator 63, a 1-bit quantizer 64 and a 1-sample delay unit 65. The addition output of the adder 62 is fed to the integrator 63 and the integration output of the integrator 63 is fed to the 1-bit quantizer 64. The quantization output of the 1-bit quantizer 64 is led out from an output terminal 66 and at the same time prefixed by a negative sign, fed back to the adder 62 by way of the 1-sample delay unit 65 and added to the analog audio signal supplied from an input terminal 61. The addition output of the adder 62 is integrated by the integrator 63. Since the integration output of the integrator 63 is quantized by the 1-bit quantizer 64 for each sampling period, it is possible to output a 1-bit quantized data, or a 1-bit audio data, from the output terminal 66.
Circuits designed for ΔΣ modulation are not technically particularly new. Such circuits have been and being popularly used in A/D converters because they can suitably be put into ICs and it is relatively easy to achieve a satisfactory level of accuracy of A/D conversion by using such a circuit. A signal subjected to ΣΔ modulation can be put back into an analog audio signal after passing it through a simple analog low-pass filter.
Meanwhile, super audio CDs (SACDs) storing 1-bit audio signals of the direct stream digital (DSD) system formed by using digital audio signals generated by the ΣΔ modulator that are weighted by “1” vs “−1” are provided with a 2-channel recording area and a multi-channel recording area that are different from each other. When multi-channel signals are reproduced by means of a 2-channel apparatus or a headphone they have to be converted into 2-channel signals by way of a down-mixing process.
Optical disc players for replaying super audio CDs are adapted to decode the data stored on the optical discs into 1-bit reproduced signals of 64 fs. A down-mixing process is used to reproduce multi-channel signals by way of 2-channels. Reproduced signals and down-mixed signals show the same rate if the down-mixing process is conducted at a rate of 64 fs.
A 1-bit signal switching processor is used for switching 1-bit audio signals of the same rate coming from the two different systems. FIG. 2 of the accompanying drawings is a schematic circuit diagram of a known 1-bit signal switching processor 70. FIG. 3 of the accompanying drawings is a flow chart illustrating the operation of the 1-bit signal switching processor 70.
The 1-bit signal switching processor 70 comprises a changeover switch 71 for switching from a reproduced signal 102 with a sampling frequency of 64 fs to a down-mixed signal 103 of 64 fs or vice versa, a mute pattern generator 73 for generating a mute pattern signal 104 with a sampling frequency of 64 fs and a controller 74 for supplying a switching control signal according to a switching request signal 101 from the system controller of an optical disc player to the mute pattern generator 73. The 1-bit signal switching processor 70 additionally comprises a cross-fade processor 72 for cross-fading a reproduced signal 102 with a sampling frequency of 64 fs into a mute pattern signal 104 with a sampling frequency of 64 fs at a rate of 64 fs, which is equal to the sampling frequency, and also cross-fading from a mute pattern signal 104 a down-mixed signal 103 with a sampling frequency of 64 fs into a reproduced signal 102 with a sampling frequency of 64 fs at a rate of 64 fs, which is equal to the sampling frequency.
The 1-bit signal switching processor 70 further comprises a first coefficient multiplier 75 for multiplying a reproduced signal 102 with a sampling frequency of 64 fs or a down-mixed signal 103 with a sampling frequency of 64 fs by the multiplication coefficient (cross-fade gain) k supplied from the controller 74 and varying the amplitude level to produce a multi-bit data, a second coefficient multiplier 76 for multiplying a mute pattern signal 104 with a sampling frequency of 64 fs generated by the mute pattern generator 73 by the coefficient (1−k) obtained by subtracting the multiplication coefficient (cross-fade gain) k supplied from the controller 74 from 1 and varying the amplitude level to produce a multi-bit data and an adder 77 for adding the multiplication output of the first coefficient multiplier 75 and the multiplication output of the second coefficient multiplier 76.
The cross-fade processor 72 by turn comprises a ΔΣ modulator 78 for conducting a re-ΔΣ modulation process on the addition output from the adder 77 and outputting a 1-bit audio data (cross-fade signal) with a sampling frequency of 64 fs and a changeover switch 79 for switching a reproduced signal 102 with a sampling frequency of 64 fs or a down-mixed signal 103 with a sampling frequency of 64 fs, the output data (cross-fade signal 105 with a sampling frequency of 64 fs) from the ΔΣ modulator 78 and the mute pattern signal 104 with a sampling frequency of 64 fs from the mute pattern generator 73 under the control of the controller 74.
Now, the operation of the 1-bit signal switching processor 70 will be described by referring to FIG. 3. Upon receiving a switching request signal 101, the cross-fade processor 72 cross-fades the 64 fs reproduced signal 102 into the mute pattern generated by the mute pattern generator 73 to smoothly switch from the 64 fs reproduced signal 102 to a 64 fs cross-fading signal 105a and then to the 64 fs mute pattern 104. The cross-fading technique that the cross-fade processor uses for a 1-bit signal that can be used here has already been patented to the applicant of this patent application (Japanese Patent No. 3318823). As a 64 fs mute pattern 104 is output, the controller 74 generates a switching signal 107 to switch the input signal from the 64 fs reproduced signal 102 to the 64 fs down-mixed signal 103. The disc player switches from the two-channel replay to the multi-channel replay. Thereafter, the cross-fade processor 72 cross-fades from the 64 fs down-mixed signal 103 into the 64 fs mute pattern signal 104 and so that the obtained 64 fs cross-fade signal 105b is smoothly switched to the 64 fs down-mixed signal 103. The cross-fade processor 72 is a switching device for switching signals with the same sampling frequency and all the processing operations are performed with 64 fs.
With an optical disc such as a super audio CD that stores ΔΣ-modulated high speed 1-bit audio signals, the mute pattern stored on the disc is reproduced as it is when the mute region is used for reproduction but it has to be switched to the mute pattern generated by the mute pattern generator when the signal reproduction is stopped.
FIG. 4 of the accompanying drawings is a schematic circuit diagram of a known 1-bit signal switching processor 80 adapted to switch to the mute pattern generated by the mute pattern generator when the signal reproduction is stopped. FIG. 5 of the accompanying drawings is a timing chart illustrating the operation of the 1-bit signal switching processor 80.
The 1-bit signal switching processor 80 comprises a mute pattern generator 81 for generating a mute pattern signal 203 with a sampling frequency of 64 fs and a controller 82 for supplying a switching control signal to cross-fade processor 83, which will be described later, according to the switching request signal 201 supplied from the system controller of the optical disc player. The cross-fade processor 83, the configuration of which will be described hereinafter, cross-fades the reproduced signal 202 with a sampling frequency of 64 fs into the mute pattern signal 203 with a sample frequency of 64 fs at a rate of 64 fs, which is equal to the sampling frequency, to generate a cross-fade signal 204.
The cross-fade processor 83 by turn comprises a first coefficient multiplier 84 for multiplying a reproduced signal 202 with a sampling frequency of 64 fs by the multiplication coefficient (cross-fade gain) k supplied from the controller 82 and varying the amplitude level to produce a multi-bit data, a second coefficient multiplier 85 for multiplying a mute pattern signal 203 with a sampling frequency of 64 fs generated by the mute pattern generator 81 by the coefficient (1−k) obtained by subtracting the multiplication coefficient (cross-fade gain) k supplied from the controller 82 from 1 and varying the amplitude level to produce a multi-bit data and an adder 86 for adding the multiplication output of the first coefficient multiplier 84 and the multiplication output of the second coefficient multiplier 85.
The cross-fade processor 83 further comprises a ΔΣ modulator 87 for conducting a re-ΔΣ modulation process on the addition output from the adder 86 and outputting a 1-bit audio data with a sampling frequency of 64 fs and a changeover switch 88 for switching a reproduced signal 202 with a sampling frequency of 64 fs, the output data (cross-fade signal 204 with a sampling frequency of 64 fs) from the ΔΣ modulator 87 and the mute pattern signal 203 with a sampling frequency of 64 fs from the mute pattern generator 81 under the control of the controller 82.
Now, the operation of the 1-bit signal switching processor 80 will be described by referring to FIG. 5. Upon receiving a switching request signal 201, the cross-fade processor 83 cross-fades the 64 fs reproduced signal 202 into the mute pattern signal 203 generated by the mute pattern generator 81 to smoothly switch from the 64 fs reproduced signal 202 to a 64 fs cross-fading signal 204 and then to the 64 fs mute pattern 203. The cross-fading technique of Japanese Patent No. 3318823 that is patented to the applicant of this patent application is used here for the cross-fade processor for cross-fading a 1-bit signal.
With an optical disc that stores ΔΣ-modulated high speed 1-bit audio signals, the mute pattern stored on the disc is reproduced as it is when the mute region is used for reproduction but it has to be switched to the mute pattern generated by the mute pattern generator when the signal reproduction is stopped. A data stored on the super audio CD is decoded to a 1-bit reproduced signal by means of a decoder at the time of signal reproduction and a mute pattern is output at the time when the signal reproduction is stopped. A 1-bit signal switching processor is sued for switching a 1-bit signal.
In the case of an optical disc such as a super audio CD provided with a 2-channel recording area and a multi-channel recording area that are different form each other, multi-channel signals have to be converted into 2-channel signals by way of a down-mixing process when they are reproduced by means of a 2-channel apparatus or a headphone as pointed out above. In high sound quality systems, the above process is conducted in a 1-bit domain and a processing technique using a rate of 128 fs, which is twice as high as the recorded sampling frequency of 64 fs, is available for improving the sound quality of the sound processed in a 1-bit domain. With this technique, it is possible to convert a multi-channel signal into a 2-channel signal with a sampling frequency of 128 fs in order to achieve a higher sound quality. On the other hand, however, the above process is not necessary when 2-channel signals are reproduced. In other words, a 2-channel signal with a sampling frequency of 64 fs needs to be reproduced directly. Thus, signals of two different types, those with a sampling frequency of 64 fs and those with a sampling frequency of 128 fs, coexist in a single system. When two different 1-bit signals are directly linked, there arises a problem that noises can appear at the boundary.
Additionally, the arrangement of FIG. 4 where the mute pattern generated by the mute pattern generator is selected when the signal reproduction is stopped entails a problem of requiring a large hardware arrangement.